In recent product development, field programmable gate arrays (FPGAs) which are easy in design variation are often used at the development stage, and functions implemented by the FPGAs are often replaced with application specific integrated circuits (ASICs) that are low in cost and high in speed for the mass production. In order to achieve effective replacement, the products are preferably designed to be suitable for the future replacement with ASICs during the development process.
In some cases, however, the FPGAs may be replaced with newly developed devices other than the ASICs intended for the replacement during the development process. The FPGAs may also be replaced with lower-cost alternatives. The replacement may require some design changes in accordance with characteristics of the devices to replace with. Such design changes usually include redesign and verification of the products in accordance with the characteristics of the newly developed devices in order to guarantee the quality of the products. For example, a PLL which outputs a plurality of clock signals may be replaced with a plurality of lower-cost PLLs each of which outputs only a single clock signal.
FIG. 21 illustrates an exemplary configuration of a PLL which outputs a plurality of clocks. That is, an example of replacement of a phase-locked loop/digital clock management (PLL/DCM; hereinafter, simply referred to as “PLL”) which outputs six clock signals (C0 to C5) with a PLL circuit which outputs six clock signals and is constituted by four serially-connected PLLs each of which outputs a clock signal. However, direct replacement with the PLL circuit may cause problems.
A technique of controlling problems caused by serially-connected PLLs, for example, an occurrence of abnormal clock signals upon resetting or turning-on, has been proposed (see, for example, Japanese Laid-open Patent Publication No. 2007-166003).
In a structure in which a PLL which outputs six clock signals is replaced directly with a PLL circuit constituted by serially-connected PLLs as illustrated in FIG. 21, however, it is possible that the PLLs might not be reset automatically at appropriate times. It is important to reset PLLs at appropriate times for those products which are desirably reset automatically without any suspension of the operation, for example, products used for communication systems.
The PLLs are reset at those times determined by monitoring lock signals output from the PLLs. The lock signal is a signal indicating the stability of the PLL, indicating whether the PLL is in a locked state or not. The lock signals of the PLL circuit are generated from each of the lock signals output from the plurality of PLLs constituting the PLL circuit. Thus, the lock signals of the PLL circuit are not always properly output due to an indefinite length of the lock signals output from each of the PLLs.